This invention relates, in general, to semiconductor devices and, more particularly, to a means and method for providing an insulating isolation wall for electrically isolating one portion of an integrated semiconductor device structure or circuit from another. The isolation wall is formed in a trench provided in the semiconductor substrate.
It is commonplace to provide isolation walls between adjacent devices or device regions in integrated circuits, particularly bipolar integrated circuits. In the prior art these isolation walls have been formed of dielectric such as silicon dioxide. A disadvantage of using thermally grown silicon dioxide for the isolation walls is that oxide growth progresses laterally as well as vertically making achievement of small lateral dimensions and precise dimensional control more difficult. In addition, trapped voids are frequently formed when oxide is used, particularly in trenches whose depth is equal to or larger than their width. Trapped voids are undesirable.
Further, silicon dioxide, which is the most commonly used trench refill material, whether grown or deposited has a different coefficient of thermal expansion than most semiconductor substrates. As a consequence, when the semiconductor wafer is heated and cooled during processing, the differential thermal expansion and contraction of the isolation wall and the substrate can induce great stress in the semiconductor substrate. The high stress leads to defect formation in the semiconductor substrate adjacent the isolation wall. This is undesirable.
It is known in the prior art to replace part of the dielectric of the isolation wall with a polycrystalline semiconductor of the same material as the substrate. The poly region is isolated from the substrate by a thin oxide region on the sides of the isolation wall trench or is doped so as to form a PN junction with the single crystal semiconductor substrate material, or both. While the use of such a polycrystalline semiconductor plug can reduce the differential expansion mismatch, it creates other problems well know in the art.
While isolation walls may be successfully made using these prior art approaches, they still suffer from a number of disadvantages. For example, the processing required to produce such prior art isolation walls is complex and expensive; it is difficult to obtain a smooth level surface above the isolation wall which joins with the substrate surface without "bird's beaks", steps, or other artifacts; the trench filling materials used for the isolation wall do not all have the desired differential stress characteristics with respect to the substrate; and trapped voids frequently form within the trench refill material. Thus, there continues to be a need for improved isolation wall structures and methods for integrated circuits and devices.
Accordingly, it is an object of the present invention to provide an improved means and method for isolation walls for semiconductor devices and integrated circuits.
It is an additional object of the present invention to provide an improved means and method for isolation walls for semiconductor devices and integrated circuits formed by etch-out and refill.
It is a further object of the present invention to provide an improved means and method for isolation walls for semiconductor devices and integrated circuits employing a material of adjustable coefficient of expansion relative to the semiconductor substrate.
It is an additional object of the present invention to provide an improved means and method for isolation walls for semiconductor devices and integrated circuits having controlled stress relative to the semiconductor substrate.
It is a further object of the present invention to provide an improved means and method for isolation walls which avoids formation of enclosed voids.
It is an additional object of the present invention to provide and improved means and method for isolation walls by use of materials and deposition techniques which provide conformal deposition of a dielectric material for filling isolation trenches.